1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to high performance CMOS memory circuits having low power read circuitry based on charge redistribution between a selected bitline pair and the internal nodes of a sense amplifier (xe2x80x9csense ampxe2x80x9d) used for sensing data.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a xe2x80x9cdesign gapxe2x80x9d between today""s electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers"" productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the xe2x80x9cdeep submicronxe2x80x9d problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other xe2x80x9cnon-logicxe2x80x9d cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (xe2x80x9cIPxe2x80x9d) componentsxe2x80x94pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that performance parameters such as access time, overall memory cycle time, power consumption, et cetera, play a pivotal role in designing a memory circuit, whether provided in an embedded SOC application or as a stand-alone device. For high performance memories, accordingly, it is desirable that each of the following constituent components of the memory cycle time is minimized as much as possible in a read operation: clock-to-wordline selection; cell-to-sense amp; and sense amp-to-output. However, minimizing the overall read cycle time requires large devices in the sense amp and column multiplex (COLMUX) circuitry, which give rise to increased power consumption. Accordingly, there exist well known trade-off constraints in the field of high performance memory design.
Because the teachings of the present invention are particularly directed to addressing these design trade-offs in the context of sense amp operations, a brief description of sense amp functionality with respect to RAMs (e.g., Static Random Access Memory or SRAM) is immediately set forth hereinbelow.
RAMs comprising a plurality of memory cells are typically configured as an array of rows and columns, with one or more I/Os (i.e., xc3x974, xc3x978, xc3x9716, etc. configurations). Also, such memories may be provided in a multi-bank architecture for applications where high speed and low power are required. Regardless of the architecture and type, each RAM cell is operable to store a single bit of information. Access to this information is facilitated by activating all memory cells in a given row (i.e., wordline or WL) and outputting the data onto bitlines associated with a selected column for providing the stored data value to the selected output. Once the data is disposed on the bitlines, voltage levels on the bitlines begin to separate to opposite power supply rails (e.g., VDD and VSS (or ground)), and a sense amp is utilized to amplify and latch the logic levels sensed on the bitlines after they are separated by a predetermined voltage difference, typically 10% or less of VDD. Furthermore, the sense amp is usually provided as a differential sense amp, with each of the memory cells providing both a DATA signal and a DATA BAR signal on the complementary bitlines (i.e., data lines) associated with each column. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value. Once a particular row and column are selected, the memory cell associated therewith is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level, typically VDD. The sense amp coupled to the two complementary bitlines senses the difference between the two bitlines once it exceeds a predetermined value and the sensed difference is indicated to the sense amp as the differing logic states of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d.
There are two common types of sense amps utilized for memory devices: one being a current mirror differential sense amp and the other being a clocked-latch type differential sense amp. It is well known that clocked-latch type sense amps are generally more advantageous than current mirror sense amps for low supply voltage, low power and deep submicron processes because they dissipate less power and work better at low voltages. Further, circuitry for implementing a clocked-latch type sense amp utilizes less area.
Even where advanced clocked-latch type sense amps are employed for memory devices, trade-offs such as speed vs. power constraints continue to plague current memory design techniques. Primarily, this is so because in traditional designs wordline pulse timing (i.e., the time period during which the selected wordline is held high) is approximately the same as the timing of COLMUX and sense amp gating switch control. On the one hand, the COLMUX and sense amp devices need to be large to ensure that the sense amp""s differential is close to bitline differential. On the other hand, it may also be necessary to reduce the device sizes so as to minimize additional load on the bitlines, to reduce substrate noise from associated diffusion, and to reduce the bitline asymmetry (which is more pronounced when larger devices are employed). In low power applications with multi-bank architectures, the trade-off becomes a critical issue since the number of physical rows in a memory bank tends to be small, wherein the bitline voltage levels move fairly rapidly.
Accordingly, the present invention advantageously provides circuitry and method for effectuating low power read operations in a memory circuit, e.g., a compilable instance having a banked architecture, wherein wordline timing is preferably decoupled from the column mux/sense amp timing so that better control of bitline differential is advantageously achieved. As a consequence, smaller geometries can be utilized for the column mux and sense amp blocks without sacrificing access time performance. Furthermore, the use of smaller devices provides better noise immunity characteristics because such devices enable the column mux/sense amp circuitry to operate as a first or second order low pass filter.
In one aspect, the present invention is directed to a low power read methodology operable with a memory circuit. When a memory read cycle is initiated with respect to a particular memory cell in a selected bank based on a plurality of address signals, a specific wordline associated with the memory cell is driven high. Upon waiting until the voltage level on the bitline coupled thereto reaches a predetermined sense level, the wordline is shut off based on a reference memory cell structure. Accordingly, the wordline stops driving the bitline after a short time period. Subsequently, after waiting for a select time, the sense amp associated with the bitline also reaches the sense level by way of charge redistribution between its internal node(s) and the bitline. The sense amp is then enabled to sense the data stored in the particular memory cell based the redistributed charge on the nodes. A bitline precharge operation takes place thereafter to equalize the bitline""s voltage prior to the following memory cycle.
In another aspect, the present invention is directed to a memory circuit having low read power capability. Preferably, the memory circuit may be provided as a compilable instance. Wordline decoder and driver circuitry is included to initiate a memory read operation with respect to a particular memory cell based on a plurality of address signals and a START signal, which START signal is dependent upon a BANK SELECT signal operable to select a particular memory bank of the memory circuit. Essentially, the wordline decoder and driver circuitry operates to drive a selected wordline associated with the particular memory cell high responsive to the plurality of address signals and the START signal. A reference wordline driver is included in the memory circuit, which driver is operable responsive at least in part to the START signal to drive a reference wordline associated with at least one reference cell structure. A pair of complementary reference bitlines coupled to the reference cell structure are operable to generate a voltage signal after a finite time has elapsed from the START signal. Further, circuitry for generating a STOP signal is also included in the memory circuit, which STOP signal is generated when the voltage signal developed on the complementary reference bitlines reaches a particular level, for example, about half of VDD level. In accordance with the teachings of the present invention, the STOP signal operates to deactivate the selected wordline and activates thereafter a sense amp operably coupled to the particular memory cell via a pair of complementary bitlines. Consequently, the wordline pulse is active only as long as is necessary to develop sufficient differential in the bitlines, which differential is transferred from the bitlines to the sense amp due to charge redistribution. Accordingly, the sense amp is preferably operable to sense the data value stored in the particular memory cell based on a charge redistribution between the sense amplifier""s internal nodes and the bitline pair after the selected wordline is deactivated.
In an exemplary embodiment of the present invention, the memory circuit preferably includes a xe2x80x9cresistivexe2x80x9d structure operable to mimic impedance and bitline resistance between the selected bitlines and sense amp. The resistive structure is operable to generate an analog sense amplifier control (ASAE) signal based on the STOP signal after a predetermined delay. Also, a capacitor structure is coupled to the resistive structure for simulating the sense amp""s capacitance. Circuitry operating responsive to the ASAE signal is provided for generating a SENSE AMPLIFIER ENABLE BAR control signal (SAEB) when the ASAE signal reaches a particular level, e.g., about half of VDD level.
In yet another aspect, the present invention is directed to a low power read operation method for a memory circuit. First, a memory read cycle is initiated with respect to a particular cell in the memory circuit based on a plurality of address signals, wherein a selected wordline associated with the particular cell is driven high. A control signal is generated thereafter based on a reference cell read operation. Responsive to the control signal, the selected wordline is deactivated thereafter. Subsequently, a sense amp operably coupled to the particular memory cell via a pair of complementary bitlines is activated, wherein the sense amp operates to latch a data value stored in the particular cell based on a charge redistribution between the sense amp""s internal nodes and the bitline pair after the selected wordline is deactivated.
In a still further aspect, the present invention is directed to a memory instance, e.g., a RAM instance, a Flash memory instance, etc., having low power read capability in a multi-bank architecture. A BANK SELECT (BST) signal is operable to select a particular memory bank of the instance, which BST signal operates as a clock for the selected bank. Circuitry is included in the memory bank for commencing a memory read cycle with respect to a particular cell in the selected bank based on a plurality of address signals and a START signal. Circuitry is also included for generating a STOP signal based on a reference cell read operation, after a selected wordline associated with is particular cell is driven high. Responsive to the STOP signal, circuitry is provided for deactivating the selected wordline after a finite amount of time. A circuit block is included for activating a sense amp operably coupled to the particular memory cell via a pair of complementary bitlines, wherein the sense amp operates to latch a data value stored in the particular cell based on a charge redistribution between the sense amp""s internal nodes and the bitline pair after the selected wordline is deactivated.
In a further exemplary embodiment, the functionality of STOP and START signals may be unified into a single control signal whereby a rising edge therein (i.e., one logic transition) is operable as one signal and a falling edge therein (i.e., the other logic transition) is operable as the other signal. Also, as a still further variation, such a control signal may be derived from the address signals themselves, wherein the rising and falling edges can be created as will be set forth in the following description.